The present invention relates in general to digital timing circuits and, more particularly, to a data hold-time indicator circuit that produces a recurring pulse width that reflects the data hold-time of an embedded register.
Parallel-to-serial converters are commonly used in digital circuit design to convert multi-bit signals to a string of data bits that are serially transmitted one at a time. One common application involves a data register embedded within an integrated circuit that periodically receives new data sourced by external logic. Timing generation logic for loading the data register is also embedded within the integrated circuit. The timing generation logic asserts a periodic signal to the external logic requesting more data be presented to the data register.
Many applications involve high speed operation, say in the gigahertz range. The data transaction must be completed within a predetermined time period. The data must be present and valid for a setup time before the data is loaded into the register by a clock signal. In addition, the data must remain present and valid for a hold-time after the transition of the clock signal. Unfortunately at such high data rates, the propagation delay uncertainty of the digital signals from the external sourcing logic are almost as long as the entire transaction period.
When the periodic signal is asserted to request more data, the external logic begins the time-consuming process of retrieving new data. When the external logic finally presents new data to the integrated circuit, the new data typically propagates through buffer logic and eventually reaches the data register. The timing generation logic asserts a clock signal to load the data register. When the data transaction is so fast that propagation delay uncertainties consume almost the entire time period, there is no guarantee that data arrives at the data register within register setup and hold-time constraints.
Since the data register and timing logic are embedded within the integrated circuit, it is difficult to directly measure the actual setup and hold-time. That is, the setup and hold-time are not readily observable by the external logic. If the data setup and hold-time cannot be observed, the data rate of the external sourcing logic must be reduced to ensure sufficient setup and hold-time. The data rate of the external sourcing logic cannot be maximized unless the actual setup and hold-time of the register is known. Otherwise, where the propagation time uncertainty consumes a large portion of the transaction time period, the data transaction may fail to correctly time the data transfer under a worst-case timing analysis.
Hence, a need exists for a circuit that provides data setup and hold-time information for embedded circuits that are otherwise unobservable.